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Structure Function
Silicon Monolithic Integrated Circuit
Voltage Regulated Charge Pump IC
Product Function
BU90030G
- Input voltage range 2.0V4.0V - PFM operation - Output voltage 4.0V (typ) - 1.5MHz(typ) switching frequency. - SSOP6 package
Absolute Maximum ratingTa=25c Item Maximum input power supply voltage Maximum input voltage Power dissipation Operating temperature range Storage temperature range Junction temperature Symbol VCC CP, CN, SHD, VOUT Pd Topr Tstg Tjmax Rating -0.3 7 -0.3 7 675 (*1) -35+85 -55+125 +125 Unit V V mW C C C
*1 When mounted on the specified PCB (70mmx70mmx1.6mm glass epoxy). Deducted by 6.75mW/c when used over Ta=25c. Operating range (Ta=25c)
Item
Symbol VBAT Cfly CCPOUT IOMAX
Rating Min. 2.0 0.1 1.0 Typ. Max. 4.0 1.0 10 80
Unit V uF uF mA
Condition
Power supply voltage
Flying Capacitor Output Capacitor Maximum Output Current
VCC=2.5V, Cfly=1.0uF, COUT=1.0uF
REV.
2/4 Electrical characteristics (unless otherwise specified VBAT=2.5[v], Ta=25[c]) Item Voltage Control part Symbol Rating Min. 3.8 3.6 Typ. 4.0 Max. 4.2 Unit Condition
Output voltage 1 Output voltage 2
Oscillator circuit MaximumOscillator frequency Output discharge circuit Discharge resistor SHD part SHD pin pull down resistor SHD pin control Operation
Vcpout1 Vcpout2
V V
Cfly=COUT=1uF VCC=2.0V, IOUT=40mA, Cfly=COUT=1.0uF VCC=2.0V, VOUT=3.8V, VOUT=40mA VCC=2.5V, VOUT=4.0V
Fosc
1.0
1.5
2.0
MHz
RDIS RSHD VSHDH VSHDL ISHD
300 100 1.4 0 -
600 200 0
900 400 4.0 0.4 5
k V V uA
voltage Non operation Circuit current Circuit current at shutdown
* No design for durability against radiation
External dimention/Pin layout
1PIN MARK
Block diagram
AR
REV.
Lot No.
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Cfly
VCC CIN CONTROL SHD ON/OFF OSC
CN
CP VOUT Driver + FET COUT
LOGIC VREF
+ -
GND
Pin number/name/function
Pin nr 1 2 3 4 5 6
Name VOUT GND SHD CN VCC CP
Function Starting charge pump output pin GND pin Shutdown pin Flying Capacitor L side input pin Power supply input pin Flying Capacitor H side input pin
Operation Notes
REV.
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1.) Absolute maximum ratings An excess in the absolute maximum rating, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2.) GND voltage The potential of GND pin must be minimum potential in all condition. As an exception, the circuit design allows voltages up to -0.3 V to be applied to the IC pin. 3.) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions 4.) Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 5.) Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction 6.) Mutual impedance Power supply and ground wiring should reflect consideration of the need to lower mutual impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 7.) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, as shown in the figures below, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. 8.) Thermal shutdown Circuit (TSD Circuit) This model IC has a built-in TSD circuit. This circuit is only to cut off the IC from thermal runaway, and has not been design to protect or guarantee the IC. in mind. 9.) External Component Use a small ESR ceramic capacitor for the external capacitor (CIN,COUT,Cfly) and set them nearby IC. Use the CIN capacitor's value that meets this condition ( CINCOUT ). ( CflyCOUT ). And Use the Cfly capacitor's value that meets this condition Therefore, the user should not plan to activate this circuit with continued operation
There may be a case that it doesn't achieve the objective characteristic because the capacity come down lower than the normal capacitor because of the bias voltage and the temperature when using a small layered ceramic capacitor. Therefore, the user should use it after checking the DC bias capacity and other characteristics.
REV.
Notice
Notes
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